The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to methods and apparatus for detecting a polishing end-point during a chemical mechanical polishing operation.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. After each layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes increasingly non-planar. This non-planar surface presents problems in the photolithographic steps of the integrated circuit fabrication process. Therefore, there is a need to periodically planarize the substrate surface.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing disk-shaped pad or belt pad. The polishing pad may be either a "standard" pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.
One problem in CMP is determining whether the polishing process is complete, i.e., whether a substrate layer has been planarized to a desired flatness or thickness. Variations in the initial thickness of the substrate layer, the slurry composition, the polishing pad condition, the relative speed between the polishing pad and the substrate, and the load on the substrate can cause variations in the material removal rate. These variations cause variations in the time needed to reach the polishing endpoint. Therefore, the polishing endpoint cannot be determined merely as a function of polishing time.
One way to determine the polishing endpoint is to remove the substrate from the polishing surface and examine it. For example, the substrate may be transferred to a metrology station where the thickness of a substrate layer is measured, e.g., with a profilometer or a resistivity measurement. If the desired specifications are not met, the substrate is reloaded into the CMP apparatus for further processing. This is a time consuming procedure that reduces the throughput of the CMP apparatus. Alternatively, the examination might reveal that an excessive amount of material has been removed, rendering the substrate unusable.
More recently, in-situ optical monitoring of the substrate has been performed, e.g., with an interferometer or reflectometer, in order to detect the polishing endpoint. For example, when polishing a metal layer to expose an underlying insulative or dielectric layer, the reflectivity of the substrate will drop abruptly when the metal layer is removed. However, as the substrate is being polished, the polishing pad condition and the slurry composition at the pad-substrate interface may change. Such changes may mask the exposure of an underlying layer, or they may imitate an endpoint condition. Thus, even when there is a sharp change in reflectivity, it may be difficult to determine the proper polishing endpoint. Moreover, endpoint detection can be even more difficult if oxide or nitride polishing is to be performed, if only planarization is being performed, if the underlying layer is to be over-polished, or if the underlying layer and the overlying layer have similar physical properties.
Another reoccurring problem in CMP is so-called "dishing" in the substrate surface. Specifically, during CMP to expose an underlying layer, when the underlying layer is exposed, the portion of a filler layer between the raised areas of the patterned underlying layer can be overpolished, creating concave depressions in the substrate surface. Dishing can render the substrate unsuitable for integrated circuit fabrication, lowering process yield.